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W986416DH 1m 4 banks 16 bits sdram publication release date: june 2001 - 1 - revision a2 general description W986416DH is a high - speed synchronous dynamic random access memory (sdram), organized as 1m words 4 banks 16 bits. using pipelined architecture and 0.175 m m process technology, W986416DH delivers a data bandwidth of up to 366m bytes per second ( - 55). for different application, W986416DH is sorted into the following speed grades : ? 55, - 6, - 7. the - 55 parts can run up to 183 mhz/cl3. the - 6 parts can run up to 166 mhz/cl3. the - 7 parts can run up to 143 mhz/cl3. for handheld device app lication, we also provide a low power option, the grade of ? 7l, with self refresh current under 400 m a and work well at 2.7v during self refresh mode. accesses to the sdram are burst oriented. consecutive memory location in one page can be accessed at a bu rst length of 1, 2, 4, 8 or full page when a bank and row is selected by an active command. column addresses are automatically generated by the sdram internal counter in burst operation. random column read is also possible by providing its address at each clock cycle. the multiple bank nature enables interleaving among internal banks to hide the precharging time. by having a programmable mode register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performa nce. W986416DH is ideal for main memory in high performance applications. features 3.3v 0.3v power supply 1048576 words 4 banks 16 bits organization sel f refresh current: standard and low power cas latency: 2 and 3 burst length: 1, 2, 4, 8, and full page sequential and interleave burst burst read, single write operation byte data controlled by dqm power - down mode auto - precharge and controlled precharge 4k refresh cycles/64 ms interface: lvttl packaged in tsop ii 54 - pin, 400 mil - 0.80 available part numbe r part number speed (cl = 3) self refresh current (max.) power supply for self r efresh mode W986416DH - 55 183 mhz 1 ma 3.0v - 3.6v W986416DH - 6 166 mhz 1 ma 3.0v - 3.6v W986416DH - 7 143 mhz 1 ma 3.0v - 3.6v W986416DH - 7l 143 mhz 400 m a 2.7v - 3.6v
w9 86416dh - 2 - pin configuration 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 ldqm cas ras cs bs0 bs1 a10/ap a0 a1 a2 a3 dq15 dq14 dq13 dq12 dq11 dq10 dq9 dq8 nc udqm clk cke nc a11 a9 a8 a7 a6 a5 a4 v cc v cc q v cc q v ss q v ss q v cc v cc v ss v ss q v cc q v ss q v cc q v ss v ss we
W986416DH publication release date: june 2001 - 3 - revision a2 pin description pin number pin name f unction description 23 ~ 26, 22, 29 ~35 a0 - a11 address multiplexed pins for row and column address. row address: a0 - a11. column address: a0 - a7. a10 is sampled during a precharge command to determine if all banks are to be precharged or bank selected by bs0, bs1. 20, 21 bs0, bs1 bank select select bank to activate during row address latch time, or bank to read/write during address latch time. 2, 4, 5, 7, 8, 10, 11, 13, 42, 44, 45, 47, 48, 50, 51, 53 dq0 - dq15 data input/ output multiplexed pins for data output and input. 19 cs chip select disable or enable the command decoder. when command decoder is disabled, new command is ignored and previous operation continues. 18 ras row address strobe command input. when sampled at the rising edge of the clock ras , cas and we define the operation to be executed. 17 cas column address strobe referred to ras 16 we write enable referred to ras 39, 15 udqm ldqm input/output mask the output buffer is placed at hi - z (with latency of 2) when dqm is sampled high in read cycle. in write cycle, sampling dqm high will block the write operation with zero latency. 38 clk clock inputs system clock used to sample inputs on the rising edge of clock. 37 cke clock enable cke controls the clock activation and deactivation. when cke is low, power down mode, suspend mode, or self refresh mode is entered. 1, 14, 27 v cc power (+3.3v) power for input buffers and logic circuit inside dram. 28, 41, 54 v ss ground ground for input buffers and logic circuit inside dram. 3, 9, 43, 49 v ccq power (+3.3v) for i/o buffer separated power from v cc , to improve dq noise immunity. 6, 12, 4 6, 52 v ssq ground for i/o buffer separated ground from v ss , to improve dq noise immunity. 36, 40 nc no connection no connection
w9 86416dh - 4 - block diagram dq0 dq15 udqm ldqm clk cke a10 clock buffer command decoder address buffer refresh counter column counter control signal generator mode register column decoder sense amplifier cell array bank #2 column decoder sense amplifier cell array bank #0 column decoder sense amplifier cell array bank #3 data control circuit dq buffer column decoder sense amplifier cell array bank #1 note: the cell array configuration is 4096 * 256 * 16 row decoder row decoder row decoder row decoder a0 a9 bs0 bs1 cs ras cas we a11
W986416DH publication release date: june 2001 - 5 - revision a2 functional descripti on power up and initialization the default power up state of the mode register is unspecified. the following power up and initialization sequence need to be followed to guarantee the device being preconditioned to each user specific needs. during power up, all v cc and v ccq pins must be ramp up simultaneously to the spe cified voltage when the input signals are held in the "nop" state. the power up voltage must not exceed v cc +0.3v on any of the input pins or v cc supplies. after power up, an initial pause of 200 m s is required followed by a precharge of all banks using th e precharge command. to prevent data contention on the dq bus during power up, it is required that the dqm and cke pins be held high during the initial pause period. once all banks have been precharged, the mode register set command must be issued to initi alize the mode register. an additional eight auto refresh cycles (cbr) are also required before or after programming the mode register to ensure proper subsequent operation. programming mode register after initial power up, the mode register set command m ust be issued for proper device operation. all banks must be in a precharged state and cke must be high at least one cycle before the mode register set command can be issued. the mode register set command is activated by the low signals of ras , cas , cs and we at the positive edge of the clock. the address input data during this cycle defines the parameters to be set as shown in the mode register operation table. a new command may be issue d following the mode register set command once a delay equal to t rsc has elapsed. please refer to the next page for mode register set cycle and operation table. bank activate command the bank activate command must be applied before any read or write opera tion can be executed. the operation is similar to ras activate in edo dram. the delay from when the bank activate command is applied to when the first read or write operation can begin must not be less than the ras to cas delay time (t rcd ). once a bank has been activated it must be precharged before another bank activate command can be issued to the same bank. the minimum time interval between successive bank activate commands to the same bank is determined by the ras cycle time of the device (t rc ). the min imum time interval between interleaved bank activate commands (bank a to bank b and vice versa) is the bank to bank delay time (t rrd ). the maximum time that each bank can be held active is specified as t ras (max.). read and write access modes after a bank has been activated, a read or write cycle can be followed. this is accomplished by setting ras high and cas low at the clock rising edge after minimum of t rcd delay. we pin voltage level defines whether the access cycle is a read operation ( we high), or a write operation ( we low). the address inputs determine the starting column address. reading or writing to a different row within an activated bank requires the bank be precharged and a new bank activate command be issued. when more than one bank is activated, interleaved bank read or write operations are possible. by using the programmed burst length and alternating the access and precharge operations between multiple b anks, seamless data access operation among many different pages can be realized. read or write commands can also be issued to the same bank or between active banks on every clock cycle.
w9 86416dh - 6 - burst read command the burst read command is initiated by applying log ic low level to cs and cas while holding ras and we high at the rising edge of the clock. the address inputs determine the starting column address for the burst. the mode register sets type of burst (sequential or interleave) and the burst length (1, 2, 4, 8, full page) during the mode register set up cycle. table 2 and 3 in the next page explain the address sequence of interleave mode and sequence mode. burst command the burst write com mand is initiated by applying logic low level to cs , cas and we while holding ras high at the rising edge of the clock. the address inputs determine the starting column address. data for the first burst write cycle must be applied on the dq pins on the same clock cycle that the write command is issued. the remaining data inputs must be supplied on each subsequent rising clock edge until the burst length is completed. data supplied to the dq pins after burst finishes will be ignored. read interrupted by a read a burst read may be interrupted by another read command. when the previous burst is interrupted, the remaining addresses are overridden by the new read address with the full burst len gth. the data from the first read command continues to appear on the outputs until the cas latency from the interrupting read command the is satisfied. read interrupted by a write to interrupt a burst read with a write command, dqm may be needed to place t he dqs (output drivers) in a high impedance state to avoid data contention on the dq bus. if a read command will issue data on the first and second clocks cycles of the write operation, dqm is needed to insure the dqs are tri - stated. after that point the w rite command will have control of the dq bus and dqm masking is no longer needed. write interrupted by a write a burst write may be interrupted before completion of the burst by another write command. when the previous burst is interrupted, the remaining a ddresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied. write interrupted by a read a read command will interrupt a burst write operation on the same clock cycle that the read comm and is activated. the dqs must be in the high impedance state at least one cycle before the new read data appears on the outputs to avoid data contention. when the read command is activated, any residual data from the burst write cycle will be ignored. bur st stop command a burst stop command may be used to terminate the existing burst operation but leave the bank open for future read or write commands to the same page of the active bank, if the burst length is full page. use of the burst stop command during other burst length operations is illegal. the burst stop command is defined by having ras and cas high with cs and we low at the rising edge of the clock. the data dqs go to a high impe dance state after a delay, which is equal to the cas latency in a burst read cycle, interrupted by burst stop. if a burst stop command is issued during a full page burst write operation, then any residual data from the burst write cycle will be ignored.
W986416DH publication release date: june 2001 - 7 - revision a2 ad dressing sequence of sequential mode a column access is performed by increasing the address from the column address which is input to the device. the disturb address is varied by the burst length as shown in table 2 . table 2 address sequence of sequential mode data access address burst length data 0 n bl = 2 (disturb address is a0) data 1 n + 1 no address carry from a0 to a1 data 2 n + 2 bl = 4 (disturb addresses are a0 and a1) data 3 n + 3 no address carry from a1 to a2 data 4 n + 4 data 5 n + 5 bl = 8 (disturb addresses are a0, a1 and a2) data 6 n + 6 no address carry from a2 to a3 data 7 n + 7 addressing sequence of interleave mode a column access is started in the input column address and is performed by inverting the address bit in the seq uence shown in table 3. table 3 address sequence of interleave mode data access address bust length data 0 a8 a7 a6 a5 a4 a3 a2 a1 a0 bl = 2 data 1 a8 a7 a6 a5 a4 a3 a2 a1 a0 data 2 a8 a7 a6 a5 a4 a3 a2 a1 a0 bl = 4 data 3 a8 a7 a6 a5 a4 a3 a2 a1 a0 data 4 a8 a7 a6 a5 a4 a3 a2 a1 a0 bl = 8 data 5 a8 a7 a6 a5 a4 a3 a2 a1 a0 data 6 a8 a7 a6 a5 a4 a3 a2 a1 a0 data 7 a8 a7 a6 a5 a4 a3 a2 a1 a0
w9 86416dh - 8 - auto - precharge command if a10 is set to high when the read or write command is issued, then the auto - precharge function is entered. during a uto - precharge, a read command will execute as normal with the exception that the active bank will begin to precharge automatically before all burst read cycles have been completed. regardless of burst length, it will begin a certain number of clocks prior to the end of the scheduled burst cycle. the number of clocks is determined by cas latency. a read or write command with auto - precharge cannot be interrupted before the entire burst operation is completed for the same bank. therefore, use of a read, write , or precharge command is prohibited during a read or write cycle with auto - precharge. once the precharge operation has started, the bank cannot be reactivated until the precharge time (t rp ) has been satisfied. issue of auto - precharge command is illegal if the burst is set to full page length. if a10 is high when a write command is issued, the write with auto - precharge function is initiated. the sdram automatically enters the precharge operation one clock delay from the last burst write cycle. this delay is referred to as write t dpl . the bank undergoing auto - precharge cannot be reactivated until t wr and t rp are satisfied. this is referred to as t dal , data - in to active delay (t dal = t wr + t rp ). when using the auto - precharge command, the interval between the b ank activate command and the beginning of the internal precharge operation must satisfy t ras (min). precharge command the precharge command is used to precharge or close a bank that has been activated. the precharge command is entered when cs , ras and we are low and cas is high at the rising edge of the clock. the precharge command can be used to precharge each bank separately or all banks simultaneously. three address bits, a10, bs0, and bs1 are used to define which bank(s) is to be precharged when the command is issued. after the precharge command is issued, the precharged bank must be reactivated before a new read or write access can be executed. the delay between the precharge command and the activate command must be greater than or equal to the precharge time (t rp ). self refresh command the self refresh command is defined by having cs , ras , cas and cke held low with we high at the rising edge of the clock. all banks must be idle prior to issuing the self refresh command. once the command is registered, cke must be held low to keep the device in self refresh mode. when the sdram has entered self refresh mode all of the external control signals, except cke, are disabled. the clock is internally disabled during self refresh operation to save power. the device will exit self refresh operation after cke is returned high. a minimum delay time is required when the device exit s self refresh operation and before the next command can be issued. this delay is equal to the t ac cycle time plus the self refresh exit time. if, during normal operation, auto refresh cycles are issued in bursts (as opposed to being evenly distributed), a burst of 4,096 auto refresh cycles should be completed just prior to entering and just after exiting the self refresh mode. power down mode the power down mode is initiated by holding cke low. all of the receiver circuits except cke are gated off to reduc e the power. the power down mode does not perform any refresh operations, therefore the device can not remain in power down mode longer than the refresh period (t ref ) of the device.
W986416DH publication release date: june 2001 - 9 - revision a2 the power down mode is exited by bringing cke high. when cke goes high, a no operation command is required on the next rising clock edge, depending on t ck . the input buffers need to be enabled with cke held high for a period equal to t cks (min.) + t ck (min.). no operation command the no operation command should be used in cases when the sdram is in a idle or a wait state to prevent the sdram from registering any unwanted commands between operations. a no operation command is registered when cs is low with ras , cas , and we held high at the rising edge of the clock. a no operation command will not terminate a previous operation that is still executing, such as a burst read or write cycle. deselect command the deselect command performs the same function as a no op eration command. deselect command occurs when cs is brought high, the ras , cas , and we signals become don't cares. clock suspend mode during normal access mode, cke must be held high ena bling the clock. when cke is registered low while at least one of the banks is active, clock suspend mode is entered. the clock suspend mode deactivates the internal clock and suspends any clocked operation that was currently being executed. there is a one clock delay between the registration of cke low and the time at which the sdram operation suspends. while in clock suspend mode, the sdram ignores any new commands that are issued. the clock suspend mode is exited by bringing cke high. there is a one cloc k cycle delay from when cke returns high to when clock suspend mode is exited.
w9 86416dh - 10 - table of operating m odes fully synchronous operations are performed to latch the commands at the positive edges of clk. table 1 shows the truth table for the operation command s. table 1 truth table (note (1), (2)) command device state cken - 1 cken dqm bs0, 1 a10 a0 - a9 cs ras cas we bank active idle h x x v v v l l h h bank precharge any h x x v l x l l h l precharge all any h x x x h x l l h l write active (3) h x x v l v l h l l write with autoprecharge active (3) h x x v h v l h l l read active (3) h x x v l v l h l h read with autoprecharge active (3) h x x v h v l h l h mode register set idle h x x v v v l l l l no - operation any h x x x x x l h h h burst stop active (4) h x x x x x l h h l device deselect any h x x x x x h x x x auto - refresh idle h h x x x x l l l h self - refresh entry idle h l x x x x l l l h self refresh exit idle (s.r) l l h h x x x x x x x x h l x h x h x x clock suspend mode entry active h l x x x x x x x x power down mode entry idle active (5) h h l l x x x x x x x x h l x h x h x h clock suspend mode exit active l h x x x x x x x x power down mode exit any (power down) l l h h x x x x x x x x h l x h x h x h data write/output enable active h x l x x x x x x x data write/output disable active h x h x x x x x x x notes: (1) v = valid, x = don't care, l = low level, h = high level (2) cken signal is input leve l when c ommands are provided. (3) these are state of bank designated by bs0, bs1 signals. (4) device state is full page burst operation. (5) power down mode can not be entered in the burst cycle. when this command asserts in the burst cycle, device state is clock suspend mode.
W986416DH publication release date: june 2001 - 11 - revision a2 simplified state diagram mode register set idle cbr refresh self refresh row active power down precharge power on active power down write write suspend writea writea suspend read suspend read reada suspend reada precharge mrs ref act cke cke cke cke cke cke cke cke cke cke self self exit cke cke write with read write auto precharge auto precharge read with write write read pre(precharge termination) pre(precharge termination) read bst bst pre manual input automatic sequence notes: mrs = mode register set ref = refresh act = active pre = precharge writea = write with auto precharge reada = read with auto precharge
w9 86416dh - 12 - dc characteristics absolute maximum rating parameter sym. ratin g unit notes input, column output voltage v in , v out - 0.3 - v cc +0.3 v 1 power supply voltage v cc, v ccq - 0.3 - 4.6 v 1 operating temperature t opr 0 - 70 c 1 storage temperature t stg - 55 - 150 c 1 soldering temperature (10s) t solder 260 c 1 power di ssipation p d 1 w 1 short circuit output current i out 50 ma 1 note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability of the device. recommended dc opera ting conditions (t a = 0 to 70 c ) parameter sym. min. typ. max. unit notes supply voltage (normal operation) v cc 3.0 3.3 3.6 v 2 supply voltage for W986416DH - 7l during self refresh mode v cc 2.7 3.3 3.6 v 2 supply voltage for i/o buffer v ccq 3.0 3.3 3.6 v 2 input high voltage v ih 2. 0 - v cc +0.3 v 2 input low voltage v il - 0.3 - 0.8 v 2 note: v ih (max.) = v cc /v cc q+1.2v for pulse width < 5 ns v il (min.) = v ss /v ss q - 1.2v for pulse width < 5 ns capacitance (v cc = 3.3v, t a = 25 c, f = 1 mhz) parameter sym. min. max. unit input capaci tance (a0 to a11, bs0, bs1, cs , ras , cas , we , dqm, cke) c i 2.5 4 pf input capacitance (clk) c clk 2.5 4 pf input/output capacitance (dq0 - dq15) c o 4 6.5 pf note: these parameters are pe riodically sampled and not 100% tested
W986416DH publication release date: june 2001 - 13 - revision a2 dc characteristics (v cc = 3.3v 0.3v, t a = 0 ~70 c) parameter sym. - 55 - 6 - 7 unit notes max. max. max. operating current t ck = min., t rc = min. active precharge command cycling without burst operation 1 bank operation i cc1 100 90 80 3 standby current t ck = min., cs = v ih v ih/l = v ih (min.)/v il (max.) cke = v ih i cc2 40 35 30 3 bank: inactive state cke = v il (power down mode) i cc2p 1 1 1 3 standby current clk = v il , cs = v ih v ih/l =v ih (min.)/v il (max.) cke = v ih i cc2s 8 8 8 bank: inactive state cke = v il (power down mode) i cc2ps 1 1 1 ma no operating current t ck = min., cs = v ih (min.) cke = v ih i cc3 65 60 55 bank: active state (4 banks) cke = v il (power down mode) i cc3p 5 5 5 burst operating current (t ck = min.) read/write command cycling i cc4 185 165 145 3, 4 auto refresh current (t ck = min.) auto refresh command cycling i cc5 125 120 110 3 standard i cc6 1 1 1 self refresh current self refresh mode (cke = 0.2v) low power i cc6l - - 400 a parameter symbol min. max. unit notes input leakage current (0v v in v cc , all other pins not under test = 0v) i i (l) - 5 5 a output leakage current (output disable, 0v v out v cc q) v o (l) - 5 5 a lvttl output 2 h 2 level voltage (i out = - 2 ma) v oh 2.4 - v lvttl output " l 2 level voltage (i out = 2 ma) v ol - 0.4 v
w9 86416dh - 14 - ac characteristics (v cc = 3.3v 0.3v, v ss = 0v, ta = 0 to 70 c) (notes: 5, 6.) parameter sym. - 55 - 6 - 7 unit note min. max. min. max. min. max. ref/active to ref/active command period trc 55 60 65 ns active to precharge command period tras 40 100000 42 100000 45 100000 active to read/write command delay time trcd 15 18 20 read/write(a) to read/write(b ) command period tccd 1 1 1 cycle precharge to active(b) command period trp 15 18 20 ns active(a) to active(b) command period trrd 11 12 14 write recovery time cl* = 2 twr 7.5 7.5 8 cl* = 3 5.5 6 7 clk cycle time cl* = 2 tck 7 .5 1000 7.5 1000 8 1000 cl* = 3 5.5 1000 6 1000 7 1000 clk high level tch 2 2 2 clk low level tcl 2 2 2 access time from clk cl* = 2 tac 5.5 5.5 6 cl* = 3 5 5 5.5 output data hold time toh 2.75 2.75 3 output data high impedance time thz 2.75 5.5 2.75 6 3 7 output data low impedance time tlz 0 0 0 power down mode entry time tsb 0 5.5 0 6 0 7 transition time of clk (rise and fall) tt 0.5 10 0.5 10 0.5 10 data - in - set - up time tds 1.5 1.5 1.5 data - in hol d time tdh 1 1 1 address set - up time tas 1.5 1.5 1.5 address hold time tah 1 1 1 cke set - up time tcks 1.5 1.5 1.5 cke hold time tckh 1 1 1 command set - up time tcms 1.5 1.5 1.5 command hold time tcmh 1 1 1 refresh t ime tref 64 64 64 ms mode register set cycle time trsc 11 12 14 ns
W986416DH publication release date: june 2001 - 15 - revision a2 notes: 1. operation exceeds "absolute maximum rating" may cause permanent damage to the devices. 2. all voltages are referenced to v ss 3. these parameters depend on the cycle rate and listed values are measured at a cycle rate with the minimum values of t ck and t rc . 4. these parameters depend on the output loading conditions. specified values are obtained with output open. 5. power up sequence (1) power up must be perform ed in the following sequence. (2) power must be applied to v cc and v cc q (simultaneously) while all input signals are held in the ?nop? state. the clk signals must be started at the same time. (3) after power - up a pause of at le ast 200 seconds is required. it is required that dqm and cke signals then be held ? high? (v cc levels) to ensure that the dq output is impedance. (4) all banks must be precharged. (5) the mode register set command must be asserted to initialize the mode register. (6) a minimum of eight auto refresh dummy cycles is required to stabilize the internal circuitry of the device. 6. ac testing conditions parameter conditions output reference level 1.4v output load see diagram below input signal levels (v ih /v il ) 2.4v/0.4v transition time (rise and fall) of input signal 1 ns input reference level 1.4v 50 ohms 1.4 v ac test load z = 50 ohms output 30pf 1. transition times are measured between v ih and v il . 2. t hz defines the time at which the outputs achieve the open circuit condition and is not referenced to output level. 3. these parameters account for the number of clock cycles and depend on the operating frequency of the clock, as follows the number of clock cycles = specified value of timing/ clock period (count fractions as whole n umber) (1) t ch is the pulse width of clk measured from the positive edge to the negative edge referenced to v ih (min.). t cl is the pulse width of clk measured from the negative edge to the positive edge referenced to v il (max.).
w9 86416dh - 16 - (2) a.c latency characteri stics cke to clock disable (cke latency) 1 cycle dqm to output to hi - z (read dqm latency) 2 dqm to output to hi - z (write dqm latency) 0 write command to input data (write data latency) 0 cs to command input ( cs la tency) 0 precharge to dq hi - z lead time cl = 2 2 cl = 3 3 precharge to last valid data out cl = 2 1 cl = 3 2 bust stop command to dq hi - z lead time cl = 2 2 cl = 3 3 bust stop command to last valid data out cl = 2 1 cl = 3 2 read with auto - precharge command to active/ref command cl = 2 bl + t rp cycle + ns cl = 3 bl + t rp write with auto - precharge command to active/ref command cl = 2 bl + t rp cl = 3 bl + t rp
W986416DH publication release date: june 2001 - 17 - revision a2 timing waveforms command input timing t ck clk a0-a10 bs0, 1 v ih v il t cmh t cms t ch t cl t t t t t cks t ckh t ckh t cks t cks t ckh cs ras cas we cke t cms t cmh t cms t cmh t cms t cmh t cms t cmh t as t ah
w9 86416dh - 18 - timing waveforms, contin ued read timing read cas latency t ac t lz t ac t oh t hz t oh burst length read command clk cs ras cas we a0-a10 bs0, 1 dq valid data-out valid data-out
W986416DH publication release date: june 2001 - 19 - revision a2 timing waveforms, continued control timing of input data *dqm2,3="l" clk (word mask) t cmh t cms t cmh t cms dqm0 t cms t cmh t cmh dqm1 dq0 -dq7 dq16 -dq23 dq8-dq15 dq24-dq31 t dh t ds t dh t ds t dh t ds t dh valid data-in valid data-in valid data-in valid data-in t ds t dh valid data-in valid data-in t dh valid data-in t dh t ds t dh t ds valid data-in valid data-in t dh valid data-in t dh valid data-in t ds t dh t ds t dh t ds valid data-in valid data-in t dh valid data-in t dh valid data-in t ds t dh t ds t dh t dh t dh t ds t ds t ds t ds dq0 -dq7 clk cke t ckh t cks t ckh t cks t ds t dh t ds t dh t dh t ds t ds t dh valid data-in valid data-in valid data-in valid data-in dq24 -dq31 dq16 -dq23 dq8 -dq15 (clock mask) t ds t dh t ds t dh t dh t ds t ds t dh valid data-in valid data-in valid data-in valid data-in t ds t dh t ds t dh t dh t ds t ds t dh valid data-in valid data-in valid data-in valid data-in t ds t dh t ds t dh t dh t ds t ds t dh valid data-in valid data-in valid data-in valid data-in t ds t ds t ds valid data-in valid data-in valid data-in t cms
w9 86416dh - 20 - timing waveforms, continued control timing of output data dq0 -dq7 valid data-out valid data-out valid data-out t oh t ac t oh t ac t oh t hz t lz t ac t oh t ac open clk (output enable) dqm0 t cmh t cms t cmh t cms t cmh t cms t cmh t cms dqm1 t oh t ac t ac t hz t ac t ac valid data-out valid data-out t oh t ac t oh t ac t oh t ac t oh dq8 -dq15 t ac t hz t lz open dq24 -dq31 dq16 -dq23 valid data-out valid data-out t oh t ac t oh t ac t oh t hz t ac t oh t ac t oh valid data-out valid data-out t oh t oh t lz t oh valid data-out valid data-out valid data-out valid data-out valid data-out t oh t ac t oh t ac t oh t ac t oh t ac valid data-out valid data-out valid data-out dq16 -dq23 t oh t ac t oh t ac t oh t ac t oh t ac valid data-out valid data-out valid data-out dq24 -dq31 t ckh t cks t ckh t cks t oh t ac t oh t ac t oh t ac t oh t ac valid data-out valid data-out valid data-out dq0 -dq7 cke clk t oh t ac t oh t ac t oh t ac t oh t ac valid data-out valid data-out valid data-out dq8 -dq15 (clock mask) *dqm2,3="l"
W986416DH publication release date: june 2001 - 21 - revision a2 timing waveforms, continued mode register set cycle a0 a1 a2 a3 a4 a5 a6 burst length addressing mode cas latency (test mode) a8 reserved a0 a7 a0 a9 a0 write mode a10 bs0 a0 a11 a0 bs1 "0" "0" a0 a3 a0 addressing mode a0 0 a0 sequential a0 1 a0 interleave a0 a9 single write mode a0 0 a0 burst read and burst write a0 1 a0 burst read and single write a0 a0 a2 a1 a0 a0 0 0 0 a0 0 0 1 a0 0 1 0 a0 0 1 1 a0 1 0 0 a0 1 0 1 a0 1 1 0 a0 1 1 1 a0 burst length a0 sequential a0 interleave 1 a0 1 a0 2 a0 2 a0 4 a0 4 a0 8 a0 8 a0 reserved a0 reserved a0 full page a0 cas latency a0 reserved a0 reserved 2 a0 3 reserved a0 a6 a5 a4 a0 0 0 0 a0 0 1 0 a0 0 1 1 a0 1 0 0 a0 0 0 1 t rsc t cms t cmh t cms t cmh t cms t cmh t cms t cmh t as t ah clk cs ras cas we a0-a10 bs0,1 register set data next command a0 reserved "0" "0" "0" "0"
w9 86416dh - 22 - operating timing exa mple interleaved bank read (burst le ngth = 4, cas latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 (clk = 100 mhz) clk dq cke dqm a0-a9 a10 we cs t rc t rc t rc t rc t ras t rp t ras t rp t rp t ras t ras t rcd t rcd t rcd t rcd t ac t ac t ac t ac t rrd t rrd t rrd t rrd active read active read active active active read read precharge precharge precharge raa rbb rac rbd rae raa caw rbb cbx rac cay rbd cbz rae aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3 cy0 cy1 cy2 cy3 bank #0 idle bank #1 bank #2 bank #3 ras cas bs1 bs0
W986416DH publication release date: june 2001 - 23 - revision a2 operating timing example, continued interleaved bank read (burst length = 4, cas latency = 3, autoprecharge) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 (clk = 100 mhz) clk cke dqm a0-a9 a10 bs1 we cas ras cs bs0 t rc t rc t rc t ras t rp t ras t rp t ras t rp t ras t rcd t rcd t rcd t ac t ac t ac t ac t rrd t rrd t rrd t rrd active read active read active active active read read t rc raa rac rbd rae dq aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3 cy0 cy1 cy2 cy3 dz0 * ap is the internal precharge start timing bank #0 idle bank #1 bank #2 bank #3 ap* ap* raa caw rbb cbx rac cay rbd rae cbz rbb ap* t rcd
w9 86416dh - 24 - operating timing example, continued interleaved bank read (burst length = 8, cas latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t rc t ras t rp t ras t rp t ras t rcd t rcd t rcd t rrd t rrd raa raa cax rbb rbb cby rac rac caz ax0 ax1 ax2 ax3 ax4 ax5 ax6 by0 by1 by4 by5 by6 by7 cz0 (clk = 100 mhz) clk dq cke dqm a0-a9 a10 bs1 we cas ras cs active read precharge active read precharge active t ac t ac read precharge t ac bank #0 idle bank #1 bank #2 bank #3 bs0
W986416DH publication release date: june 2001 - 25 - revision a2 operating t iming example, continued interleaved bank read (burst length = 8, cas latency = 3, autoprecharge) a0-a9 bank #0 idle bank #1 bank #2 bank #3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t rc t ras t rp t ras t rcd t rcd t rcd t rrd t rrd ax0 ax1 ax2 ax3 ax4 ax5 ax6 ax7 by0 by1 by4 by5 by6 cz0 raa raa cax rbb rbb cby (clk = 100 mhz) rac rac caz * ap is the internal precharge start timing active read active active read t cac t cac t cac clk dq cke dqm a10 we cas ras cs read ap* ap* bs1 bs0
w9 86416dh - 26 - operating timing example, continued interleaved bank write (burst length = 8) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t rc t ras t rp t ras t rcd t rcd t rcd t rrd t rrd raa raa cax rbb rbb cby rac rac caz ax0 ax1 by4 by5 by6 by7 cz0 cz1 cz2 (clk = 100 mhz) write precharge active active write precharge active write clk dq cke dqm a0-a9 a10 bs1 we cas ras cs idle bank #0 bank #1 bank #2 bank #3 bs0 ax4 ax5 ax6 ax7 by0 by1 by2 by3
W986416DH publication release date: june 2001 - 27 - revision a2 operating timing example, continued interleaved bank write (burst leng th = 8, autoprecharge) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t rc t ras t rp t ras t rcd t rcd t rcd t rrd t rrd raa raa cax rbb rbb cby rab rac ax0 ax1 ax4 ax5 ax6 ax7 by0 by1 by2 by3 by4 by5 by6 by7 cz0 cz1 cz2 caz (clk = 100 mhz) * ap is the internal precharge start timing clk dq cke dqm a0-a9 a10 bs1 we cas ras cs active write write active bank #0 idle bank #1 bank #2 bank #3 ap* active write ap* bs0
w9 86416dh - 28 - operating timing example, continued page mode read (burst length = 4, cas latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t ccd t ccd t ccd t ras t ras t rcd t rcd t rrd raa raa cai rbb rbb cbx cay cam cbz a0 a1 a2 a3 bx0 bx1 ay0 ay1 ay2 am0 am1 am2 bz0 bz1 bz2 bz3 (clk = 100 mhz) * ap is the internal precharge start timing clk dq cke dqm a0-a9 a10 bs1 we cas ras cs active read active read read read read precharge t ac t ac t ac t ac t ac bank #0 idle bank #1 bank #2 bank #3 ap* bs0
W986416DH publication release date: june 2001 - 29 - revision a2 operating timing example, continued page mode read/write (burst length = 8, cas latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t ras t rcd t wr raa raa cax cay ax0 ax1 ax2 ax3 ax4 ax5 ay1 ay0 ay2 ay4 ay3 q q q q q q d d d d d (clk = 100 mhz) clk dq cke dqm a0-a9 a10 bs1 we cas ras cs active read write precharge t ac bank #0 idle bank #1 bank #2 bank #3 bs0
w9 86416dh - 30 - operating timing example, continued au toprecharge read (burst length = 4, cas latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 (clk = 100 mhz) clk dq cke dqm a0-a9 a10 we cas ras cs bs1 t rc t ras t rp t ras t rcd t rcd t ac t ac active read ap* active read ap* raa rab raa caw rab cax aw0 aw1 aw2 aw3 * ap is the internal precharge start timing bank #0 idle bank #1 bank #2 bank #3 bs0 bx0 bx2 bx1 bx3
W986416DH publication release date: june 2001 - 31 - revision a2 operating timing example, continued autoprecharge write (burst length = 4) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 (clk = 100 mhz) clk dq cke dqm a0-a9 a10 we cas ras cs bs1 t rc t rc t rp t ras t rp raa t rcd t rcd rab rac raa rab cax rac bx0 bx1 bx2 bx3 active active write ap* active write ap* * ap is the internal precharge start timing bank #0 idle bank #1 bank #2 bank #3 t ras bs0 caw aw0 aw1 aw2 aw3
w9 86416dh - 32 - operating timing example, continued autorefresh cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 (clk = 100 mhz) all banks prechage auto refresh auto refresh (arbitrary cycle) t rc t rp t rc clk dq cke dqm a0-a9 a10 we cas ras cs bs0,1
W986416DH publication release date: june 2001 - 33 - revision a2 operating timing example, continued self - refresh cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 (clk = 100 mhz) clk dq cke dqm a0-a9 a10 bs0,1 we cas ras cs t cks t sb t cks t cks all banks precharge self refresh entry arbitrary cycle t rp self refresh cycle t rc no operation cycle
w9 86416dh - 34 - operating timing example, continued bust read and single write (burst length = 4, cas latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 clk (clk = 100 mhz) q q q q d d d q q q q read read single write active bank #0 idle bank #1 bank #2 bank #3 cs ras cas we bs1 a10 a0-a9 dqm cke dq t rcd rba rba cbv cbw cbx cby cbz av0 av1 av2 av3 aw0 ax0 ay0 az0 az1 az2 az3 t ac t ac bs0
W986416DH publication release date: june 2001 - 35 - revision a2 operating timing example, continued power - down mode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 (clk = 100 mhz) raa caa raa cax raa raa ax0 ax1 ax2 ax3 t sb t cks t cks t cks t sb t cks active standby power down mode precharge standby power down mode active nop precharge nop active note: the powerdown mode is entered by asserting cke "low". all input/output buffers (except cke buffers) are turned off in the powerdown mode. when cke goes high, command input must be no operation at next clk rising edge. clk dq cke dqm a0-a9 a10 bs we cas ras cs read
w9 86416dh - 36 - operating timing example, continued auto - precharge timing (write cycle) d0 write act ap 0 11 10 9 8 7 6 5 4 3 2 1 d0 d0 d0 d0 ap act d1 ap act d1 d1 d2 d2 d3 d3 d4 d5 d6 d7 ap act ap act ap act d1 d0 ap act d1 d2 d3 ap act d0 d1 d2 d3 d4 d5 d6 d7 write write write write write write write d0 (1) cas latency=2 (2) cas latency=3 write act ap when the auto precharge command is asserted, the period from bank activate command to the start of internal precgarging must be at least tras (min.) represents the write with auto precharge command. represents the start of internal precharging. represents the bank activate command. note: t rp t wr t rp t wr t rp t wr t rp t wr t rp t wr t rp t wr t rp t wr t rp t wr ( a ) burst length = 1 command ( b ) burst length = 2 command ( c ) burst length = 4 command ( d ) burst length = 8 command dq dq dq dq ( a ) burst length = 1 command ( b ) burst length = 2 command ( c ) burst length = 4 command ( d ) burst length = 8 command dq dq dq dq
W986416DH publication release date: june 2001 - 37 - revision a2 operating timing ex ample, continued auto - precharge timing (read cycle) read ap 0 11 10 9 8 7 6 5 4 3 2 1 q0 q0 read ap act q1 read ap act q1 q2 ap act read act q0 q3 (1) cas latency=2 read act ap when the auto precharge command is asserted, the period from bank activate command to the start of internal precgarging must be at least t ras (min). represents the read with auto precharge command. represents the start of internal precharging. represents the bank activate command. note: t rp t rp t rp ( a ) burst length = 1 command ( b ) burst length = 2 command ( c ) burst length = 4 command ( d ) burst length = 8 command dq dq dq dq q0 q1 q2 q3 q4 q5 q6 q7 t rp q0 read ap act q0 read ap act q1 q0 read ap act q1 q2 q3 read ap act q0 q1 q2 q3 q4 q5 q6 q7 (2) cas latency=3 t rp t rp t rp t rp ( a ) burst length = 1 command ( b ) burst length = 2 command ( c ) burst length = 4 command ( d ) burst length = 8 command dq dq dq dq
w9 86416dh - 38 - operating timing example, continued timing chart of read to write cycle note: the output data must be masked by dqm to avoid i/o conflict. read write 11 10 9 8 7 6 5 4 3 2 1 read read read write write d0 d1 d2 d3 write dq dq ( a ) command 0 dq dq dqm ( b ) command dqm ( b ) command dqm dqm d0 d1 d2 d3 d0 d1 d2 d3 d0 d1 d2 d3 (1) cas latency=2 ( a ) command (2) cas latency=3 in the case of burst length = 4
W986416DH publication release date: june 2001 - 39 - revision a2 operating timing example, continued timing chart of write to read cycle 0 11 10 9 8 7 6 5 4 3 2 1 in the case of burst length = 4 q0 read q1 q2 q3 read write write d0 d1 dq dq ( a ) command ( b ) command dqm dqm (2) cas latency = 3 q0 q1 q2 q3 d0 read write read write q0 q1 q2 q3 q0 q1 q2 q3 ( a ) command dq dq dqm ( b ) command dqm (1) cas latency = 2 d0 d0 d1
w9 86416dh - 40 - operating timing example, continued timing ch art of burst stop cycle (burst stop command) read bst 0 11 10 9 8 7 6 5 4 3 2 1 dq dq q0 q1 q2 q3 q0 q1 q2 q3 read bst ( a ) cas latency =2 command ( b ) cas latency = 3 command (3) read cycle q4 q4 dq d0 d1 d2 d3 write bst command (2) write cycle d4 note: represents the burst stop command bst
W986416DH publication release date: june 2001 - 41 - revision a2 operating timing example, continued timing chart of burst stop cycle (precharge command) in the case of burst lenght = 8 note: represents the precharge command prcg read prcg 0 11 10 9 8 7 6 5 4 3 2 1 q0 q1 q2 q3 q0 q1 q2 q3 read prcg q4 q4 ( a )cas latency =2 ( b )cas latency = 3 dq dq (1) read cycle (2) write cycle commad commad write prcg d0 d1 d2 d3 d0 d1 d2 d3 write prcg d4 d4 ( b ) cas latency = 3 dq ( a ) cas latency =2 dqm dqm dq t wr t wr commad commad
w9 86416dh - 42 - operating timing example, continued cke/dqm input timing (write cycle) 7 6 5 4 3 2 1 cke mask ( 1 ) d1 d6 d5 d3 d2 clk cycle no. external internal cke dqm dq 7 6 5 4 3 2 1 ( 2 ) d1 d6 d5 d3 d2 clk cycle no. external internal cke dqm dq 7 6 5 4 3 2 1 ( 3 ) d1 d6 d5 d4 d3 d2 clk cycle no. external cke dqm dq dqm mask dqm mask cke mask cke mask internal clk clk clk
W986416DH publication release date: june 2001 - 43 - revision a2 operating timing example, continued c ke/dqm input timing (read cycle) 7 6 5 4 3 2 1 ( 1 ) q1 q6 q4 q3 q2 clk cycle no. external internal cke dqm dq open open 7 6 5 4 3 2 1 q1 q6 q3 q2 clk cycle no. external internal cke dqm dq open ( 2 ) 7 6 5 4 3 2 1 q1 q6 q3 q2 clk cycle no. external internal cke dqm dq q5 q4 ( 3 ) q4 clk clk clk
w9 86416dh - 44 - operating timing example, continued self refresh/power down mode exit timing asynchronous control input buffer turn on time (power down mode exit time) is specified by command nop clk cke command a ) t ck < t cks (min.) + t ck (min.) input buffer enable command clk cke command b) t ck >= t cks (min.) + t ck (min.) input buffer enable note: command nop all input buffer (include clk buffer) are turned off in the power down mode and self refresh mode represents the no-operation command represents one command t ck t ck t cks (min) +t ck (min) t cks (min) +t ck (min) cks t (min.) + t ck (min.)
W986416DH publication release date: june 2001 - 45 - revision a2 package dimensions 54l tsop (ii) - 400 mil seating plane e d a2 a1 a e b zd 1 27 54 28 h e y l c l1 zd 0.71 0.028 0.002 0.009 max. min. nom. a2 b a a1 0.24 1.00 0.05 0.40 1.20 0.15 sym. dimension (mm) max. min. nom. e 0.80 0.0315 0.016 l 0.40 0.50 0.60 0.020 0.024 0.396 e 10.06 10.16 10.26 0.400 0.404 0.871 d 22.22 22.12 22.62 0.875 0.905 0.039 0.016 0.047 0.006 dimension (inch) 0.10 0.004 0.32 l1 0.80 0.032 c 0.15 0.006 0.012 0.455 11.76 11.56 11.96 0.463 0.471 h e y 0.10 0.004 controlling dimension: millimeters
w9 86416dh - 46 - headquarters no. 4, creation rd. iii, science - based industrial park, hsinchu, taiwan tel: 886 - 3 - 5770066 fax: 886 - 3 - 5792766 http://www.winbond.com.tw/ voice & fax - on - demand: 886 - 2 - 27197006 taipei office 11f, no. 115, sec. 3, min - sheng east rd., taipei, taiwan tel: 886 - 2 - 27190505 fax: 886 - 2 - 27197502 winbond electronics (h.k.) ltd. unit 9 - 15, 22f, millennium city, no. 378 kwun tong rd; kowloon, hong kong tel: 852 - 27513100 fax: 852 - 27552064 winbond electronics north america corp. winbond memory lab. winbond microelectronics corp. winbond systems lab. 2727 n. first street, san jose, ca 95134, u.s.a. tel: 408 - 9436666 fax: 408 - 5441798 headquarters no. 4, creation rd. iii, science - based industrial park, hsinchu, taiwan tel: 886 - 3 - 5770066 fax: 886 - 3 - 5792766 http://www.winbond.com.tw/ voice & fax - on - demand: 886 - 2 - 27197006 taipei office 11f, no. 115, sec. 3, min - sheng east rd., taipei, taiwan tel: 886 - 2 - 27190505 fax: 886 - 2 - 27197502 winbond electronics (h.k.) ltd. unit 9 - 15, 22f, millennium city, no. 378 kwun tong rd; kowloon, hong kong tel: 852 - 27513100 fax: 852 - 27552064 winbond electronics north america corp. winbond memory lab. winbond microelectronics corp. winbond systems lab. 2727 n. first street, san jose, ca 95134, u.s.a. tel: 408 - 9436666 fax: 408 - 5441798 note: all data and specifications are subject to change without notice.

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